As the scale of integrated circuits has decreased, a number of new techniques have been introduced to the manufacturing process. One of these is the use of Anti-Reflective Layers (ARLs). These include both grown or deposited varieties, such as Titanium Nitride (TiN) or a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL), and coatings, such as an Anti-Reflective Coating (ARC).
The purpose of the ARL is to reduce net linewidth variations in the photolithographic process. Variations that are allowable within a 1 μm or even 0.6 λm process become unacceptable as devices move deeper into the submicron range. A variation of, for example, ±0.1 μm or even ±0.15 μm in Critical Dimension (CD) may be tolerable at 1 μm, but would produce a factor of 2 or 3 difference between the upper and lower values at the 0.3 μm scale. Such variations in transistor gate length can undermine device performance and reliability, particularly on the low side. An ARL layer can readily reduce such variations in CD width by a third when compared to the same process without this layer.
The ARL is an additional step included as part of the photolithographic process. It is a highly absorbing film formed directly on the substrate and upon which the photoresist then is formed. The ARL absorbs most of the radiation that penetrates the resist, generally in the 70-85% range. Standing waves are thereby substantially reduced as there is less reflection off the substrate, and scattering from topological features is also suppressed. In addition, as an ARL partially planarizes the wafer topology, resist thickness is more uniform and linewidth variation over steps is improved.
This effect is shown in FIG. 1, where CD in units of μm is plotted against resist thickness in units of Angstroms. The shown data points are for a set of reference structures formed to measure variations in critical dimension. The lower line, with data points indicated by a series of xs, corresponds to a series of dense features without the use of an ARL. This curve is very sensitive to variations in resist thickness and shows a periodic structure due to standing waves.
The top three lines show the use of an ARL. The line formed on the solid squares corresponds to the same dense features as the non-ARL line of xs and may be compared directly. The ARL line varies in a much smoother fashion than the non-ARL curve and is therefore far less sensitive to processing variations. The line of open triangles, corresponding to isolated features with the same structure as solid squares, and the line of solid circles, corresponding to a different structure, also show the uniformity produced by using an anti-reflective layer.
As is often the case with process technology, the solution to one problem often creates a new problem, or, in this case, causes a latent problem to manifest itself. The particular problem here is the ability to integrate a high performance capacitor into a standard CMOS process flow, where capacitor performance is defined in terms of stability over a wide voltage range and low leakage levels.
A more or less standard embodiment of a portion of this process flow can be given by the following series of steps:
Standard Transistor Flow                1. Lower electrode deposition        2. Lower electrode doping        3. Lower electrode anneal        
Capacitor Process Module                4. Capacitor dielectric deposition        5. Upper electrode deposition        6. Upper electrode implant        7. Upper electrode anneal        8. Photo mask to define upper electrode        9. Upper electrode etch        10. Capacitor dielectric removal        
Standard Transistor Flow continued                11. ARL formation        12. Photo mask to define lower electrode        13. Lower electrode etch        14. Poly oxidation for transistor and subsequent steps, where the subsequent steps would include the standard fabrication steps, such as masking and implantation to form the transistors' source and drain, as well as any common but optional steps, such as, say, the formation of a Lightly Doped Drain (LDD). Some of the steps on this list are themselves optional but common, such as the anneal of steps 3 and 7 or, what is more pertinent here, step 11.        
This list of steps is broken into three parts. Steps 1-3 are common to both the formation of transistors for the device as well as the capacitors. If the capacitors were not needed, the process would proceed directly from step 3 to step 11 for the ARL to be applied and steps 4-10 eliminated. The inclusion of steps 4-10 allows the fabrication of a high-performance capacitor to be integrated into this standard CMOS process flow. In this way, these steps can be added as a group, or module, when the device being fabricated requires capacitors and otherwise deleted without changing the non-capacitor, transistor steps or flow. A variation could define and etch the lower electrode before the capacitor dielectric is formed, but it is preferred to integrate this with the etch of the standard transistor flow, particularly at 0.35 μm and below.
Step 4 forms a dielectric for the capacitors, such as an oxide, an Oxide-Nitride-Oxide (ONO) sandwich, oxynitride, or one of the other standard variations. Steps 5-9 form the upper electrodes, the lower electrodes having been formed, but not defined, at the same time as those for the transistors in steps 1-3. The capacitor dielectric remains at the end of step 9. This dielectric could be left at this stage and step 10 eliminated, its removal being incorporated into step 13 when the lower electrodes are etched. This modification would, however, require a revision of steps 12 and 13, as having this extra layer still on the substrate would change the reflectivity of the stack. The various settings for all the process parameters would then need to be recalibrated accordingly. Aside from the practical difficulties and complexities this modification would introduce, it would also mean that steps 4-10 were no longer an independent “module” that could be inserted or deleted depending on device requirements. For this reason, step 10 is included for ease of integration into the standard CMOS process.
Step 11 follows and is included for the reasons described earlier. It is an optional step and introduces an added layer of complexity to the process. For this reason it is normally omitted for device near or above the micron level, but is increasingly standard as devices move ever deeper into the submicron range.
The problem in this process as found in the prior art is in the juxtaposition of step 10 with step 11. It is this combination of the dielectric removal with the application of an anti-reflective layer having poor insulation properties that is detrimental to the capacitors.
This problem is that step 10 not only removes the unwanted capacitor dielectric, but will also undercut into the wanted portion below the upper electrode. This situation is shown in FIG. 3, which represents the process through step 10. This shows an undefined lower electrode layer 120 upon a field oxide or other underlying layers 130 included to isolate the lower electrode layer 120 electrically. An upper electrode 140 has been defined and etched, and is separated from the lower electrode layer 120 by a dielectric layer 160. Ideally, the dielectric layer 160 would have its sides even with those of the upper electrode. Instead, it suffers from the undercutting indicated at locations 180.
If processing were to continue as is common in a 1 μm or even 0.6 μm process, namely, without the ARL of step 11, this would not cause any major problems. In this case, steps 12 and 13 define and etch the lower electrode immediately after step 10, and are themselves followed by the formation of the transistor oxide in step 14. At this point, again with step 11 absent, this undercutting 180 will have been filled back in by a non-conductor such as borophosphosilicate glass (BPSG), a silicate glass, and degradation of the capacitors' dielectric will be minimal or non-existent.
This is demonstrated in FIGS. 10 and 11, where the solid diamonds represent this process without the ARL of step 11. FIG. 10 shows cumulative probability vs. capacitor leakage current at 5 volts, with the horizontal scale logarithmic in units of fA/μm2. For the process without an anti-reflective layer, this is a nearly vertical line at a value of 10−1.5≈0.03 fA/μm2. FIG. 11 is a plot of cumulative probability vs. capacitor voltage coefficient. This is a measure of capacitance as a function of the voltage across its plates. For an idealized conducting electrode capacitor, capacitance is independent of voltage, and the graph would be a vertical line at 0. For a capacitor formed on a semiconductor device, the plates of the capacitor are now of doped silicon or similar material and the deviation from this ideal is measured in PPM per volt. The line should still be as vertical as possible, for device consistency, and as close to zero as possible, for the best performance of the individual capacitors. The solid diamonds of the non-ARL process are again nearly vertical, and with a magnitude of just over 20 PPM/V, the negative values show how the coefficient is defined. This set of points, the solid diamonds, can be seen as reference values against which a fully integrated process can be measured.
With the inclusion of both steps 10 and 11, this undercutting is now filled in by the less benign ARL. In particular, PEARL is a silicon-rich SixONy film and is expected to be a poor insulator, resulting in high leakage currents. This will greatly degrade both device performance, due to leakage well beyond design specifications, and stability, as variations in performance will vary over a wide voltage range of values as the amount of undercutting 180 will vary from capacitor to capacitor. This is shown on FIGS. 10 and 11 by the solid squares. In FIG. 10, these points are well to the right of the reference values with leakage currents of, at best, several orders of magnitude higher. In FIG. 11, these points are far from vertical, showing a capacitance that is very voltage dependent due to excessive leakage.
Even when the undercutting, 180 of FIG. 3, is minimized or eliminated by using, for example, a dry etch in step 10, the combination of step 10 with step 11 can still cause capacitor degradation. Although the ARL no longer intrudes significantly into the inter-electrode region, its proximity still affects performance if the ARL is not sufficiently insulating, as is the case for PEARL.
Therefore, it is an objective of the present invention to integrate a high performance capacitor into a CMOS process flow, particularly where the flow incorporates an anti-reflective layer to reduce variations in critical dimension width.